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staging: gpib: Add TNT4882 chip based GPIB driver
Driver for National Instruments TNT4882 based boards Signed-off-by: Dave Penkler <dpenkler@gmail.com> Link: https://lore.kernel.org/r/20240918121908.19366-22-dpenkler@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Dave Penkler
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
0dc1ad1c00
commit
0cd5b05551
7
drivers/staging/gpib/tnt4882/Makefile
Normal file
7
drivers/staging/gpib/tnt4882/Makefile
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@@ -0,0 +1,7 @@
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ccflags-$(CONFIG_GPIB_PCMCIA) := -DGPIB_PCMCIA
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obj-m += tnt4882.o
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tnt4882-objs := tnt4882_gpib.o mite.o
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221
drivers/staging/gpib/tnt4882/mite.c
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221
drivers/staging/gpib/tnt4882/mite.c
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@@ -0,0 +1,221 @@
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// SPDX-License-Identifier: GPL-2
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/*
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* Hardware driver for NI Mite PCI interface chip,
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* adapted from COMEDI
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*
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* Copyright (C) 1997-8 David A. Schleef
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* Copyright (C) 2002 Frank Mori Hess
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*
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* The PCI-MIO E series driver was originally written by
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* Tomasz Motylewski <...>, and ported to comedi by ds.
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*
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* References for specifications:
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*
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* 321747b.pdf Register Level Programmer Manual (obsolete)
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* 321747c.pdf Register Level Programmer Manual (new)
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* DAQ-STC reference manual
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*
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* Other possibly relevant info:
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*
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* 320517c.pdf User manual (obsolete)
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* 320517f.pdf User manual (new)
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* 320889a.pdf delete
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* 320906c.pdf maximum signal ratings
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* 321066a.pdf about 16x
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* 321791a.pdf discontinuation of at-mio-16e-10 rev. c
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* 321808a.pdf about at-mio-16e-10 rev P
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* 321837a.pdf discontinuation of at-mio-16de-10 rev d
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* 321838a.pdf about at-mio-16de-10 rev N
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "mite.h"
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#define PCI_MITE_SIZE 4096
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#define PCI_DAQ_SIZE 4096
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struct mite_struct *mite_devices;
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#define TOP_OF_PAGE(x) ((x) | (~(PAGE_MASK)))
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void mite_init(void)
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{
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struct pci_dev *pcidev;
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struct mite_struct *mite;
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for (pcidev = pci_get_device(PCI_VENDOR_ID_NATINST, PCI_ANY_ID, NULL);
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pcidev;
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pcidev = pci_get_device(PCI_VENDOR_ID_NATINST, PCI_ANY_ID, pcidev)) {
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mite = kmalloc(sizeof(*mite), GFP_KERNEL);
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if (!mite)
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return;
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memset(mite, 0, sizeof(*mite));
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mite->pcidev = pcidev;
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pci_dev_get(mite->pcidev);
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mite->next = mite_devices;
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mite_devices = mite;
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}
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}
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int mite_setup(struct mite_struct *mite)
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{
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u32 addr;
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if (pci_enable_device(mite->pcidev)) {
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pr_err("mite: error enabling mite.\n");
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return -EIO;
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}
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pci_set_master(mite->pcidev);
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if (pci_request_regions(mite->pcidev, "mite")) {
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pr_err("mite: failed to request mite io regions.\n");
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return -EIO;
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};
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addr = pci_resource_start(mite->pcidev, 0);
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mite->mite_phys_addr = addr;
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mite->mite_io_addr = ioremap(addr, pci_resource_len(mite->pcidev, 0));
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if (!mite->mite_io_addr) {
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pr_err("mite: failed to remap mite io memory address.\n");
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return -ENOMEM;
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}
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pr_info("mite: 0x%08lx mapped to %p\n", mite->mite_phys_addr, mite->mite_io_addr);
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addr = pci_resource_start(mite->pcidev, 1);
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mite->daq_phys_addr = addr;
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mite->daq_io_addr = ioremap(mite->daq_phys_addr, pci_resource_len(mite->pcidev, 1));
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if (!mite->daq_io_addr) {
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pr_err("mite: failed to remap daq io memory address.\n");
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return -ENOMEM;
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}
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pr_info("mite: daq: 0x%08lx mapped to %p\n", mite->daq_phys_addr, mite->daq_io_addr);
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writel(mite->daq_phys_addr | WENAB, mite->mite_io_addr + MITE_IODWBSR);
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mite->used = 1;
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return 0;
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}
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void mite_cleanup(void)
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{
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struct mite_struct *mite, *next;
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for (mite = mite_devices; mite; mite = next) {
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next = mite->next;
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if (mite->pcidev)
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pci_dev_put(mite->pcidev);
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kfree(mite);
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}
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}
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void mite_unsetup(struct mite_struct *mite)
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{
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if (!mite)
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return;
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if (mite->mite_io_addr) {
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iounmap(mite->mite_io_addr);
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mite->mite_io_addr = NULL;
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}
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if (mite->daq_io_addr) {
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iounmap(mite->daq_io_addr);
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mite->daq_io_addr = NULL;
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}
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if (mite->mite_phys_addr) {
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pci_release_regions(mite->pcidev);
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pci_disable_device(mite->pcidev);
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mite->mite_phys_addr = 0;
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}
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mite->used = 0;
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}
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void mite_list_devices(void)
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{
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struct mite_struct *mite, *next;
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pr_info("Available NI PCI device IDs:");
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if (mite_devices)
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for (mite = mite_devices; mite; mite = next) {
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next = mite->next;
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pr_info(" 0x%04x", mite_device_id(mite));
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if (mite->used)
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pr_info("(used)");
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}
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pr_info("\n");
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}
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int mite_bytes_transferred(struct mite_struct *mite, int chan)
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{
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int dar, fcr;
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dar = readl(mite->mite_io_addr + MITE_DAR + CHAN_OFFSET(chan));
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fcr = readl(mite->mite_io_addr + MITE_FCR + CHAN_OFFSET(chan)) & 0x000000FF;
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return dar - fcr;
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}
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int mite_dma_tcr(struct mite_struct *mite)
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{
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int tcr;
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int lkar;
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lkar = readl(mite->mite_io_addr + CHAN_OFFSET(0) + MITE_LKAR);
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tcr = readl(mite->mite_io_addr + CHAN_OFFSET(0) + MITE_TCR);
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MDPRINTK("lkar=0x%08x tcr=%d\n", lkar, tcr);
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return tcr;
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}
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void mite_dma_disarm(struct mite_struct *mite)
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{
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int chor;
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/* disarm */
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chor = CHOR_ABORT;
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writel(chor, mite->mite_io_addr + CHAN_OFFSET(0) + MITE_CHOR);
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}
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void mite_dump_regs(struct mite_struct *mite)
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{
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void *addr = 0;
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unsigned long temp = 0;
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pr_info("mite address is =0x%p\n", mite->mite_io_addr);
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addr = mite->mite_io_addr + MITE_CHOR + CHAN_OFFSET(0);
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pr_info("mite status[CHOR]at 0x%p =0x%08lx\n", addr, temp = readl(addr));
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//mite_decode(mite_CHOR_strings,temp);
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addr = mite->mite_io_addr + MITE_CHCR + CHAN_OFFSET(0);
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pr_info("mite status[CHCR]at 0x%p =0x%08lx\n", addr, temp = readl(addr));
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//mite_decode(mite_CHCR_strings,temp);
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addr = mite->mite_io_addr + MITE_TCR + CHAN_OFFSET(0);
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pr_info("mite status[TCR] at 0x%p =0x%08x\n", addr, readl(addr));
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addr = mite->mite_io_addr + MITE_MCR + CHAN_OFFSET(0);
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pr_info("mite status[MCR] at 0x%p =0x%08lx\n", addr, temp = readl(addr));
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//mite_decode(mite_MCR_strings,temp);
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addr = mite->mite_io_addr + MITE_MAR + CHAN_OFFSET(0);
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pr_info("mite status[MAR] at 0x%p =0x%08x\n", addr, readl(addr));
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addr = mite->mite_io_addr + MITE_DCR + CHAN_OFFSET(0);
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pr_info("mite status[DCR] at 0x%p =0x%08lx\n", addr, temp = readl(addr));
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//mite_decode(mite_CR_strings,temp);
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addr = mite->mite_io_addr + MITE_DAR + CHAN_OFFSET(0);
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pr_info("mite status[DAR] at 0x%p =0x%08x\n", addr, readl(addr));
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addr = mite->mite_io_addr + MITE_LKCR + CHAN_OFFSET(0);
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pr_info("mite status[LKCR]at 0x%p =0x%08lx\n", addr, temp = readl(addr));
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//mite_decode(mite_CR_strings,temp);
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addr = mite->mite_io_addr + MITE_LKAR + CHAN_OFFSET(0);
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pr_info("mite status[LKAR]at 0x%p =0x%08x\n", addr, readl(addr));
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addr = mite->mite_io_addr + MITE_CHSR + CHAN_OFFSET(0);
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pr_info("mite status[CHSR]at 0x%p =0x%08lx\n", addr, temp = readl(addr));
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//mite_decode(mite_CHSR_strings,temp);
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addr = mite->mite_io_addr + MITE_FCR + CHAN_OFFSET(0);
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pr_info("mite status[FCR] at 0x%p =0x%08x\n\n", addr, readl(addr));
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}
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243
drivers/staging/gpib/tnt4882/mite.h
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243
drivers/staging/gpib/tnt4882/mite.h
Normal file
@@ -0,0 +1,243 @@
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/* SPDX-License-Identifier: GPL-2 */
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/*
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* Hardware driver for NI Mite PCI interface chip
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*
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* Copyright (C) 1999 David A. Schleef <ds@stm.lbl.gov>
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*/
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#ifndef _MITE_H_
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#define _MITE_H_
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#include <linux/pci.h>
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#define PCI_VENDOR_ID_NATINST 0x1093
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//#define DEBUG_MITE
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#ifdef DEBUG_MITE
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#define MDPRINTK(format, args...) pr_debug(format, ## args)
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#else
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#define MDPRINTK(args...)
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#endif
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#define MITE_RING_SIZE 3000
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struct mite_dma_chain {
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u32 count;
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u32 addr;
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u32 next;
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};
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struct mite_struct {
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struct mite_struct *next;
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int used;
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struct pci_dev *pcidev;
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unsigned long mite_phys_addr;
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void *mite_io_addr;
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unsigned long daq_phys_addr;
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void *daq_io_addr;
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int DMA_CheckNearEnd;
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struct mite_dma_chain ring[MITE_RING_SIZE];
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};
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extern struct mite_struct *mite_devices;
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extern inline unsigned int mite_irq(struct mite_struct *mite)
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{
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return mite->pcidev->irq;
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};
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extern inline unsigned int mite_device_id(struct mite_struct *mite)
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{
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return mite->pcidev->device;
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};
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void mite_init(void);
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void mite_cleanup(void);
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int mite_setup(struct mite_struct *mite);
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void mite_unsetup(struct mite_struct *mite);
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void mite_list_devices(void);
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int mite_dma_tcr(struct mite_struct *mite);
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void mite_dma_arm(struct mite_struct *mite);
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void mite_dma_disarm(struct mite_struct *mite);
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void mite_dump_regs(struct mite_struct *mite);
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void mite_setregs(struct mite_struct *mite, unsigned long ll_start, int chan, int dir);
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int mite_bytes_transferred(struct mite_struct *mite, int chan);
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#define CHAN_OFFSET(x) (0x100 * (x))
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/* DMA base for chan 0 is 0x500, chan 1 is 0x600 */
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#define MITE_CHOR 0x500
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#define CHOR_DMARESET BIT(31)
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#define CHOR_SET_SEND_TC BIT(11)
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#define CHOR_CLR_SEND_TC BIT(10)
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#define CHOR_SET_LPAUSE BIT(9)
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#define CHOR_CLR_LPAUSE BIT(8)
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#define CHOR_CLRDONE BIT(7)
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#define CHOR_CLRRB BIT(6)
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#define CHOR_CLRLC BIT(5)
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#define CHOR_FRESET BIT(4)
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#define CHOR_ABORT BIT(3)
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#define CHOR_STOP BIT(2)
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#define CHOR_CONT BIT(1)
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#define CHOR_START BIT(0)
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#define CHOR_PON (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE)
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#define MITE_CHCR 0x504
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#define CHCR_SET_DMA_IE BIT(31)
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#define CHCR_CLR_DMA_IE BIT(30)
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#define CHCR_SET_LINKP_IE BIT(29)
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#define CHCR_CLR_LINKP_IE BIT(28)
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#define CHCR_SET_SAR_IE BIT(27)
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#define CHCR_CLR_SAR_IE BIT(26)
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#define CHCR_SET_DONE_IE BIT(25)
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#define CHCR_CLR_DONE_IE BIT(24)
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#define CHCR_SET_MRDY_IE BIT(23)
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#define CHCR_CLR_MRDY_IE BIT(22)
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#define CHCR_SET_DRDY_IE BIT(21)
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#define CHCR_CLR_DRDY_IE BIT(20)
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#define CHCR_SET_LC_IE BIT(19)
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#define CHCR_CLR_LC_IE BIT(18)
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#define CHCR_SET_CONT_RB_IE BIT(17)
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#define CHCR_CLR_CONT_RB_IE BIT(16)
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#define CHCR_FIFODIS BIT(15)
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#define CHCR_FIFO_ON 0
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#define CHCR_BURSTEN BIT(14)
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#define CHCR_NO_BURSTEN 0
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#define CHCR_NFTP(x) ((x) << 11)
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#define CHCR_NFTP0 CHCR_NFTP(0)
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#define CHCR_NFTP1 CHCR_NFTP(1)
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#define CHCR_NFTP2 CHCR_NFTP(2)
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#define CHCR_NFTP4 CHCR_NFTP(3)
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#define CHCR_NFTP8 CHCR_NFTP(4)
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#define CHCR_NFTP16 CHCR_NFTP(5)
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#define CHCR_NETP(x) ((x) << 11)
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#define CHCR_NETP0 CHCR_NETP(0)
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#define CHCR_NETP1 CHCR_NETP(1)
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#define CHCR_NETP2 CHCR_NETP(2)
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#define CHCR_NETP4 CHCR_NETP(3)
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#define CHCR_NETP8 CHCR_NETP(4)
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#define CHCR_CHEND1 BIT(5)
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#define CHCR_CHEND0 BIT(4)
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#define CHCR_DIR BIT(3)
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#define CHCR_DEV_TO_MEM CHCR_DIR
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#define CHCR_MEM_TO_DEV 0
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#define CHCR_NORMAL ((0) << 0)
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#define CHCR_CONTINUE ((1) << 0)
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#define CHCR_RINGBUFF ((2) << 0)
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#define CHCR_LINKSHORT ((4) << 0)
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#define CHCR_LINKLONG ((5) << 0)
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#define CHCRPON (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | \
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CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | \
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CHCR_CLR_LC_IE | CHCR_CLR_CONT_IE)
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#define MITE_TCR 0x508
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/* CR bits */
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#define CR_RL(x) ((x) << 21)
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#define CR_RL0 CR_RL(0)
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#define CR_RL1 CR_RL(1)
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#define CR_RL2 CR_RL(2)
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#define CR_RL4 CR_RL(3)
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#define CR_RL8 CR_RL(4)
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#define CR_RL16 CR_RL(5)
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#define CR_RL32 CR_RL(6)
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#define CR_RL64 CR_RL(7)
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#define CR_RD(x) ((x) << 19)
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#define CR_RD0 CR_RD(0)
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#define CR_RD32 CR_RD(1)
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#define CR_RD512 CR_RD(2)
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#define CR_RD8192 CR_RD(3)
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#define CR_REQS(x) ((x) << 16)
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#define CR_REQSDRQ0 CR_REQS(4)
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#define CR_REQSDRQ1 CR_REQS(5)
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#define CR_REQSDRQ2 CR_REQS(6)
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#define CR_REQSDRQ3 CR_REQS(7)
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#define CR_ASEQX(x) ((x) << 10)
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#define CR_ASEQX0 CR_ASEQX(0)
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#define CR_ASEQDONT CR_ASEQX0
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#define CR_ASEQXP1 CR_ASEQX(1)
|
||||
#define CR_ASEQUP CR_ASEQXP1
|
||||
#define CR_ASEQXP2 CR_ASEQX(2)
|
||||
#define CR_ASEQDOWN CR_ASEQXP2
|
||||
#define CR_ASEQXP4 CR_ASEQX(3)
|
||||
#define CR_ASEQXP8 CR_ASEQX(4)
|
||||
#define CR_ASEQXP16 CR_ASEQX(5)
|
||||
#define CR_ASEQXP32 CR_ASEQX(6)
|
||||
#define CR_ASEQXP64 CR_ASEQX(7)
|
||||
#define CR_ASEQXM1 CR_ASEQX(9)
|
||||
#define CR_ASEQXM2 CR_ASEQX(10)
|
||||
#define CR_ASEQXM4 CR_ASEQX(11)
|
||||
#define CR_ASEQXM8 CR_ASEQX(12)
|
||||
#define CR_ASEQXM16 CR_ASEQX(13)
|
||||
#define CR_ASEQXM32 CR_ASEQX(14)
|
||||
#define CR_ASEQXM64 CR_ASEQX(15)
|
||||
#define CR_PSIZEBYTE BIT(8)
|
||||
#define CR_PSIZEHALF (2 << 8)
|
||||
#define CR_PSIZEWORD (3 << 8)
|
||||
#define CR_PORTCPU (0 << 6)
|
||||
#define CR_PORTIO BIT(6)
|
||||
#define CR_PORTVXI (2 << 6)
|
||||
#define CR_PORTMXI (3 << 6)
|
||||
#define CR_AMDEVICE BIT(0)
|
||||
|
||||
#define CHSR_INT 0x80000000
|
||||
#define CHSR_DONE 0x02000000
|
||||
#define CHSR_LINKC 0x00080000
|
||||
|
||||
#define MITE_MCR 0x50c
|
||||
#define MCRPON 0
|
||||
|
||||
#define MITE_MAR 0x510
|
||||
|
||||
#define MITE_DCR 0x514
|
||||
#define DCR_NORMAL BIT(29)
|
||||
#define DCRPON 0
|
||||
|
||||
#define MITE_DAR 0x518
|
||||
|
||||
#define MITE_LKCR 0x51c
|
||||
|
||||
#define MITE_LKAR 0x520
|
||||
#define MITE_LLKAR 0x524
|
||||
#define MITE_BAR 0x528
|
||||
#define MITE_BCR 0x52c
|
||||
#define MITE_SAR 0x530
|
||||
#define MITE_WSCR 0x534
|
||||
#define MITE_WSER 0x538
|
||||
#define MITE_CHSR 0x53c
|
||||
#define MITE_FCR 0x540
|
||||
|
||||
#define MITE_FIFO 0x80
|
||||
#define MITE_FIFOEND 0xff
|
||||
|
||||
#define MITE_AMRAM 0x00
|
||||
#define MITE_AMDEVICE 0x01
|
||||
#define MITE_AMHOST_A32_SINGLE 0x09
|
||||
#define MITE_AMHOST_A24_SINGLE 0x39
|
||||
#define MITE_AMHOST_A16_SINGLE 0x29
|
||||
#define MITE_AMHOST_A32_BLOCK 0x0b
|
||||
#define MITE_AMHOST_A32D64_BLOCK 0x08
|
||||
#define MITE_AMHOST_A24_BLOCK 0x3b
|
||||
|
||||
enum mite_registers {
|
||||
MITE_IODWBSR = 0xc0, //IO Device Window Base Size Register
|
||||
MITE_CSIGR = 0x460, //chip signature
|
||||
MITE_IODWBSR_1 = 0xc4, // IO Device Window Base Size Register 1 (used by 6602 boards)
|
||||
MITE_IODWCR_1 = 0xf4
|
||||
};
|
||||
|
||||
enum MITE_IODWBSR_bits {
|
||||
WENAB = 0x80, // window enable
|
||||
WENAB_6602 = 0x8c // window enable for 6602 boards
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
1874
drivers/staging/gpib/tnt4882/tnt4882_gpib.c
Normal file
1874
drivers/staging/gpib/tnt4882/tnt4882_gpib.c
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user