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PCI/ASPM: Enable only L0s and L1 for devicetree platforms

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f3ac2ff148 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree
platforms") enabled Clock Power Management and L1 PM Substates, but those
features depend on CLKREQ# and possibly other device-specific
configuration.  We don't know whether CLKREQ# is supported, so we shouldn't
blindly enable Clock PM and L1 PM Substates.

Enable only ASPM L0s and L1, and only when both ends of the link advertise
support for them.

Fixes: f3ac2ff148 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms")
Reported-by: Christian Zigotzky <chzigotzky@xenosoft.de>
Link: https://lore.kernel.org/r/db5c95a1-cf3e-46f9-8045-a1b04908051a@xenosoft.de/
Reported-by: FUKAUMI Naoki <naoki@radxa.com>
Closes: https://lore.kernel.org/r/22594781424C5C98+22cb5d61-19b1-4353-9818-3bb2b311da0b@radxa.com/
Reported-by: Herve Codina <herve.codina@bootlin.com>
Link: https://lore.kernel.org/r/20251015101304.3ec03e6b@bootlin.com/
Reported-by: Diederik de Haas <diederik@cknow-tech.com>
Closes: https://lore.kernel.org/r/DDJXHRIRGTW9.GYC2ULZ5WQAL@cknow-tech.com/
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Tested-by: Diederik de Haas <diederik@cknow-tech.com>
Acked-by: Dragan Simic <dsimic@manjaro.org>
Link: https://patch.msgid.link/20251023180645.1304701-1-helgaas@kernel.org
This commit is contained in:
Bjorn Helgaas
2025-10-23 13:06:26 -05:00
parent f294a5fd34
commit df5192d9bb
1 changed files with 9 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
drivers/pci/pcie/aspm.c
View File

@@ -243,8 +243,7 @@ struct pcie_link_state {
/* Clock PM state */
u32 clkpm_capable:1; /* Clock PM capable? */
u32 clkpm_enabled:1; /* Current Clock PM state */
u32 clkpm_default:1; /* Default Clock PM state by BIOS or
override */
u32 clkpm_default:1; /* Default Clock PM state by BIOS */
u32 clkpm_disable:1; /* Clock PM disabled */
};
@@ -376,18 +375,6 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
pcie_set_clkpm_nocheck(link, enable);
}
static void pcie_clkpm_override_default_link_state(struct pcie_link_state *link,
int enabled)
{
struct pci_dev *pdev = link->downstream;
/* For devicetree platforms, enable ClockPM by default */
if (of_have_populated_dt() && !enabled) {
link->clkpm_default = 1;
pci_info(pdev, "ASPM: DT platform, enabling ClockPM\n");
}
}
static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
{
int capable = 1, enabled = 1;
@@ -410,7 +397,6 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
}
link->clkpm_enabled = enabled;
link->clkpm_default = enabled;
pcie_clkpm_override_default_link_state(link, enabled);
link->clkpm_capable = capable;
link->clkpm_disable = blacklist ? 1 : 0;
}
@@ -811,19 +797,17 @@ static void pcie_aspm_override_default_link_state(struct pcie_link_state *link)
struct pci_dev *pdev = link->downstream;
u32 override;
/* For devicetree platforms, enable all ASPM states by default */
/* For devicetree platforms, enable L0s and L1 by default */
if (of_have_populated_dt()) {
link->aspm_default = PCIE_LINK_STATE_ASPM_ALL;
if (link->aspm_support & PCIE_LINK_STATE_L0S)
link->aspm_default |= PCIE_LINK_STATE_L0S;
if (link->aspm_support & PCIE_LINK_STATE_L1)
link->aspm_default |= PCIE_LINK_STATE_L1;
override = link->aspm_default & ~link->aspm_enabled;
if (override)
pci_info(pdev, "ASPM: DT platform, enabling%s%s%s%s%s%s%s\n",
FLAG(override, L0S_UP, " L0s-up"),
FLAG(override, L0S_DW, " L0s-dw"),
FLAG(override, L1, " L1"),
FLAG(override, L1_1, " ASPM-L1.1"),
FLAG(override, L1_2, " ASPM-L1.2"),
FLAG(override, L1_1_PCIPM, " PCI-PM-L1.1"),
FLAG(override, L1_2_PCIPM, " PCI-PM-L1.2"));
pci_info(pdev, "ASPM: default states%s%s\n",
FLAG(override, L0S, " L0s"),
FLAG(override, L1, " L1"));
}
}