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Falcon engines have two distinct register bases: `PFALCON` and `PFALCON2`. So far we assumed that `PFALCON2` was located at `PFALCON + 0x1000` because that is the case of most engines, but there are exceptions (NVDEC uses `0x1c00`). Fix this shortcoming by leveraging the redesigned relative registers definitions to assign a distinct `PFalcon2Base` base address to each falcon engine. Reviewed-by: Lyude Paul <lyude@redhat.com> Link: https://lore.kernel.org/r/20250718-nova-regs-v2-16-7b6a762aa1cd@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
20 lines
463 B
Rust
20 lines
463 B
Rust
// SPDX-License-Identifier: GPL-2.0
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use crate::falcon::{FalconEngine, PFalcon2Base, PFalconBase};
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use crate::regs::macros::RegisterBase;
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/// Type specifying the `Sec2` falcon engine. Cannot be instantiated.
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pub(crate) struct Sec2(());
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impl RegisterBase<PFalconBase> for Sec2 {
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const BASE: usize = 0x00840000;
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}
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impl RegisterBase<PFalcon2Base> for Sec2 {
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const BASE: usize = 0x00841000;
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}
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impl FalconEngine for Sec2 {
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const ID: Self = Sec2(());
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}
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